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What's needed is not more hardware but better algorithms to utilize that hardware. some of this is achievable in the obvious ways (more execution units, wider decode, etc) but only with very low returns to that hardware. there remains a substantial degree of IPC improvement available In other words, IMHO (and of course I could be wrong, but this is informed speculation, not wishful thinking) As far as I can tell (which is limited, as I say, because there do not seem to be any good studies tracking the issues that really matter) this is the next frontier in wide OoO, given that Apple has implemented everything that's lower lying fruit. If you DO track instruction criticality, you can then start to do things like ensure that only the critical instructions sit in expensive high performance scheduling queues, while the bulk of non-critical instructions can sit in cheaper buffers. those limit studies did a poor job of investigating THIS particular issue.Ī different way to tackle the problem is by tracking instruction criticality and the consequences that flow from this. the last serious limit studies were done 30 years ago on designs that you wouldn't want to put into a lightbulb today We know that, IN THEORY, there is a lot of such parallelism, but This is basically a question of how deep your dispatch/issue scheduling queues are (as opposed to everything else like ROB depth).

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In other words, the extent to which you can get these independent runs executing together (and thus utilizing your full width) depends on how far you look ahead in the instruction stream relative to current execution. these are interleaved with other independent runs of dependent instructions there are runs of dependent instructions BUT You can get some info on the Intel side (for example the paper I have referred to occasionally on how a few hard to predict branches dominate branch misprediction, and should be handled via other means).īut there are successor issues, in particular:

Those are all (in principle) easy to track, even so I'm unaware of any serious investigation of them for Apple's design. Why might a CPU not run at full width every cycle? It's hard to say anything informed because no-one is providing the sorts of information that would be required.

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